EL5042

Topics

1. error/warning
2. Diagnostics
3. Offset LSB Bit [Bit] (0x80p8:17)
4. SSI

error/warning/not ready

Could be caused by:

• Wrong settings (bit counts, ..), see further below on this page (and also motion/best practice).
• Bad electrical connection
• Wrong power supply
• Defect encoder or EL5042
• Long cabling lengths
• Wrong communication frequency

Always start troubleshooting by checking the error, warning and ready bits and reading the EL5042 manual. Next step is to read the diagnostic SDO bits of the EL5042, see below under heading “Diagnostics”.

Bad electrical connection

The serial communication is handled by two RS422 channels, one for the clock and one for data. These channels can be measured with a scope:

• The clock should output periodic “bursts” with clock pulses with a short break in between. The bursts should appear in the same rate as the ethercat frame rate (EC_RATE, default 1kHz). And the frequency of the clock pulses should correspond with the setting in your startup script (normally 250kHz..10Mhz depending on configuration)
• The data channel should return bits in sync with the clock pulses.

Lack of clock or data pulses could be caused by (in order of probability):

1. short circuit or error in cabling
2. defect/burt encoder
3. No/wrong power supply
4. defect EL5042 (if lack of clock pulses)

Wrong power supply

Make sure the encoder is powered with the correct voltage. Most encoders require 5V, but there are also some that require 9V, 12V or 24V.

The EL5042 can supply 5V or 9V. The default setting is 5V and in order to change the setting to 9V a special sequence need to be executed (see below and the EL5042 manual).

From EL5042 manual:

#     Setting the encoder supply voltage
#        Condition: To write 0x8008:12 “Supply Voltage”, the value 0x72657375 (ASCII: “user”) must be set in 0xF008 “Code word”.
#
#        Set the value into index 0x8008:12 “Supply Voltage” (Specification in steps of 0.1 V).
#        Only the values 50 (5.0 V) and 90 (9.0 V) are permissible.
#        This setting applies to both channels.
#        Before switching to 9.0 V make sure that both BiSS encoders support the extended voltage range!
#
#        The encoder supply voltage is set for both channels in object 0x8008:12
#  --------------------------------------------------------------------------------------------------------------------------

After the above sequence is executed, the slave must go to INIT state before the new setting is applied. This can be done with the ethercat tool:

ethercat states -m<master_id> -p<slave_id> INIT
# then back to preop
ethercat rescan

After ensuring that the encoder is correctly supplied, then verify the power consumption of the encoder and compare with the specified consumption. If the power consumption does not match, the encoder might be broken or a faulty cabling.

Long cable lengths

Long cable lengths can affect both power supply levels and the serial data channels.

Power supply:

Longer cables will normally also result in a higher voltage drops. Especially for 5V encoders this can be an issue. Make sure that the voltage are within the specified range by measuring the voltage level close to the encoder.

If the voltage is to low (mainly for 5V encoders):

1. Can cabling length be reduced
2. Can cable impedance be reduced (higher area)
3. Add a separate (5V) power supply with possibilities to adjust the voltage level to a slightly higher voltage. Make sure the voltage is not too high at the encoder end.

Serial communication:

The serial communication is also affected by the cable length. For long cable lengths a reduction of the clock rate can be needed. The clock rate can be reduced by setting the CLK_FRQ_KHZ macro in the call to applyComponent.cmd (set clock freq. to 500kHz):

${SCRIPTEXEC} ${ecmccomp_DIR}applyComponent.cmd "COMP=Encoder-RLS-LA11-26bit-BISS-C,CH_ID=1,MACROS='CLK_FRQ_KHZ=500'"

For EL5042 the following rates are available:

• 10 MHz
• 5 MHz
• 3.33 MHz
• 2.5 MHz default for some encoders in ecmccomp
• 2 MHz
• 1 MHz Max for SSI and default for some encoders in ecmccomp
• 500 kHz
• 250 kHz

NOTE: The closest freq. equal or higher than CLK_FRQ_KHZ will be selected.

Wrong communication frequency

In ecmccfg the default frequency for encoders are set to the lowest possible value, 100kHz. Sometimes increaseing the frequence to 1MHz will result in a more stable reading. If possible use ecmccomp instead of ecmccfg for configutration of encoders since, in the ecmccomp repo, the default frequency values are higher and normally more stable.

See above for available communications rates.

Diagnostics

The diagnostic data can be read from register Index A0p8 FB BiSS-C Diag data (for Ch.1, p = 0; Ch.2, p = 1):

The ecmccfg/utils/read_el5042_diag.sh tool can be used for reading the diagnostics:

bash read_el5042_diag.sh <master_id> <slave_id> <channel_id>

NOTE: The channel id starts at 0. First encoder channel is 0.

Example: master 1, slave 14, channel 0

# first login to ecmc server
$ bash read_el5042_diag.sh 1 14 0

#########################################################
Reading EL5042 Ch 0 status at master id 1 and slave id 14:

Power supply present:
0x01 1
Error:
0x00 0
SDC Error:
0x01 1
WD Error:
0x01 1
Data valid:
0x00 0
Data raw value:
0x0000000000000000 0

#########################################################

Note: The tool ecmccfg/utils/PDO_read can also be used for reading the diagnostics.

Offset LSB Bit [Bit] (0x80p8:17)

When using the LSB offset setting, the same amount of bits needs to be subtracted from the ST_BITS or MT_BITS

Example: 26bit RLS, no LSB offset

${SCRIPTEXEC} ${ecmccomp_DIR}applyComponent.cmd "COMP=Encoder-RLS-LA11-26bit-BISS-C,CH_ID=1,OFF_BITS=0"

Example: 26bit RLS with 3 bits offset (ST_BITS=23, OFF_BITS=0)

#If the offset is needed then the sum of the bit's still need to match the bit-count of the encoder. Example: Offset 3 LSB bits, set ST_BITS=23 (26-3)
${SCRIPTEXEC} ${ecmccomp_DIR}applyComponent.cmd "COMP=Encoder-Generic-BISS-C,CH_ID=1,MACROS=MT_BITS=0,ST_BITS=23,CLK_FRQ_KHZ=1000,OFF_BITS=3"

SSI

• The entire SSI frame needs to covered in MT_BITS and ST_BITS (also status bits and startup bits), also see “Offset LSB Bit” above.
• Enabling status bits by SDO (0x80p8:02) will not work, seems only valid for BISS-C (kind of hints this in manual).

Example: 26bit RLS encoder with 2 status bits (set ST_BITS=28)

${SCRIPTEXEC} ${ecmccomp_DIR}applyComponent.cmd "COMP=Encoder-Generic-SSI,CH_ID=1,MACROS=MT_BITS=0,ST_BITS=28,CLK_FRQ_KHZ=1000,CODING=0"

Some SSI encoders, i.e. Posital kit SSI, also send startup bits. These also needs to be accounted for in the ST_BITS and MT_BITS.

Example: Posital kit SSI encoder, KCD-S1X3B-1617-IE4F-GRQ

# Specs:
#    Single turn bits 17
#    Multiturn bits: 16
#    Status bits: 2
#    Startup bits 8 (zeros)
# This then results in: 
#     MT_BITS=16 + 8 = 24  (multi turn bits + startup bits) 
#     ST_BITS=17 + 2 = 19  (single turn bits + status bits) 
${SCRIPTEXEC} ${ecmccomp_DIR}applyComponent.cmd "COMP=Encoder-Generic-SSI,CH_ID=1,MACROS=MT_BITS=24,ST_BITS=19"

The status bits can then be masked away by:

1. Using the LSB offset (set to 2 and reduce ST_BITS to 26), then the status bits are shifted away already in EL5042 hardware. Then you cannot access the status bits (to use from PLC or for interlock)
2. Setting a mask in axis yaml file (encoder.mask: 0xFFFFFFC), in this case the encoder.absBits should not be used because it’s automatically calculated by the mask command. Then you can reach the bits in the raw encoder value.